i965/gen6: Manipulate state batches for HiZ meta-ops [v4]

i965/gen6: Manipulate state batches for HiZ meta-ops [v4]

A lot of the state manipulation is handled by the meta-op state setup.
However, some batches need manual intervention.

v2:
   Do not special-case the 3DSTATE_DEPTH_STENCIL.Depth_Test_Enable bit
   for HiZ in gen6_upload_depth_stencil(). The HiZ meta-op sets
   ctx->Depth.Test, just read the value from that.

v3:
   Add a new dirty flag, BRW_STATE_HIZ, for brw_tracked_state. Flag it
   immediately before and after executing the HiZ operation in
   gen6_resolve_slice(). Add the flag to the the dirty bits for the
   following state packets:
      gen6_clip_state
      gen6_depth_stencil_state
      gen6_sf_state
      gen6_wm_state

v4:
   - Add BRW_NEW_STATE_HIZ to the dirty bit table in brw_state_upload.c.
     This is needed for INTEL_DEBUG=state.
   - Align brw dirty bit for gen6_depth_stencil_state.

Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>