litescope/bridge: create a generic wishbone bridge that can be used with different...
authorFlorent Kermarrec <florent@enjoy-digital.fr>
Fri, 1 May 2015 15:42:00 +0000 (17:42 +0200)
committerFlorent Kermarrec <florent@enjoy-digital.fr>
Fri, 1 May 2015 15:51:18 +0000 (17:51 +0200)
commit1281a463d6c959f67741fc17ffe5d7ed4078c02b
treee6061c8202852f58c34cb804086a0a5c003c3388
parent23126415d361b60c8a0034064637d39529bb8870
litescope/bridge: create a generic wishbone bridge that can be used with different phys (the phy needs to provide a sink/source with 8bits data).

- we can now pass a phy to LiteScopeWishboneBridge
- LiteScopeUART2Wishbone is only a specific LiteScopeWishboneBridge
- UART mux is removed since complicated and no longer useful (we can now create easily virtual UART over Ethernet, USB or PCIe) or simply add another UART for debug.
12 files changed:
misoclib/com/liteeth/example_designs/targets/base.py
misoclib/com/liteeth/example_designs/test/make.py
misoclib/com/litepcie/example_designs/targets/dma.py
misoclib/com/litepcie/example_designs/test/make.py
misoclib/mem/litesata/example_designs/targets/bist.py
misoclib/mem/litesata/example_designs/test/bist.py
misoclib/mem/litesata/example_designs/test/make.py
misoclib/tools/litescope/bridge/uart2wb.py [deleted file]
misoclib/tools/litescope/bridge/wishbone.py [new file with mode: 0644]
misoclib/tools/litescope/example_designs/targets/simple.py
misoclib/tools/litescope/example_designs/test/make.py
misoclib/tools/litescope/host/driver/uart.py