Fixed supply0/supply1 with many wires
authorClifford Wolf <clifford@clifford.at>
Thu, 11 Dec 2014 12:56:20 +0000 (13:56 +0100)
committerClifford Wolf <clifford@clifford.at>
Thu, 11 Dec 2014 12:56:20 +0000 (13:56 +0100)
commit1282a113da11351dbac2b9df53e3e430d12def4a
tree161579a1c17417785fa2e389de991768ab99b3fd
parent032511fac854cd0507dc84242bb55508c4757441
Fixed supply0/supply1 with many wires
frontends/verilog/verilog_parser.y