Fix handling of Verilog ~& and ~| operators
authorClifford Wolf <clifford@clifford.at>
Thu, 1 Jun 2017 10:43:21 +0000 (12:43 +0200)
committerClifford Wolf <clifford@clifford.at>
Thu, 1 Jun 2017 10:43:21 +0000 (12:43 +0200)
commit129984e115d318e00ec065ea76cb8c5926393bc4
treeab29b5dc3b1cddc386e3f4653a31c96f65562cc0
parent0290b68a44b815cb852393ebcb16b1e15948a90e
Fix handling of Verilog ~& and ~| operators
frontends/verilog/verilog_parser.y