Merge pull request #2188 from antmicro/missing-operators
authorwhitequark <whitequark@whitequark.org>
Fri, 26 Jun 2020 07:30:27 +0000 (07:30 +0000)
committerGitHub <noreply@github.com>
Fri, 26 Jun 2020 07:30:27 +0000 (07:30 +0000)
commit12c016ebdc61d3eba681579e7b0b4d81672e498f
treea4b2953cb6ea25865915721b71d2f22a1e06f725
parentd6bdc09422e89c30207810cf00021b9ea37991e7
parent39c39848a21dc4f4a2c3b17842d854047ba6c16f
Merge pull request #2188 from antmicro/missing-operators

Add logic-assignments operators
frontends/verilog/verilog_parser.y