Fixed parsing of verilog macros at end of line
authorClifford Wolf <clifford@clifford.at>
Sat, 18 Jan 2014 18:22:20 +0000 (19:22 +0100)
committerClifford Wolf <clifford@clifford.at>
Sat, 18 Jan 2014 18:22:20 +0000 (19:22 +0100)
commit13359d65ba8cc4a968b5b27deef4040fb2430899
treee2c13af344ae5fedbef42cb362159b2ad2123b5d
parent2fbaaaca7af79a6505679092251a80dc89cbc493
Fixed parsing of verilog macros at end of line
frontends/verilog/preproc.cc