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(parent: d80f4a4) | patch
mem-ruby: add cache hit/miss statistics for TCP and TCC
authorKyle Roarty <kyleroarty1716@gmail.com>
Wed, 10 Jun 2020 22:20:44 +0000 (17:20 -0500)
committerKyle Roarty <kyleroarty1716@gmail.com>
Sat, 20 Jun 2020 04:20:45 +0000 (04:20 +0000)
commit1339a1b08014311d4fd443d9a26b632a2438d7f7
tree1d56ca2dff2ddf998fddb4b3e64e7c176132c9c5tree
parentd80f4a40045c8fe261fd7bc016bb045acb755efbcommit | diff
mem-ruby: add cache hit/miss statistics for TCP and TCC

Change-Id: Ifa6fdbb9dd062a3684b9620eac6683c57e651a72
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30174
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bradford Beckmann <brad.beckmann@amd.com>
Maintainer: Bradford Beckmann <brad.beckmann@amd.com>
src/mem/ruby/protocol/GPU_VIPER-TCC.sm diff | blob | history
src/mem/ruby/protocol/GPU_VIPER-TCP.sm diff | blob | history