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(parent: d6cb981) | patch
fhdl/verilog: fix representation of negative integers
authorSebastien Bourdeauducq <sebastien@milkymist.org>
Wed, 11 Dec 2013 21:26:10 +0000 (22:26 +0100)
committerSebastien Bourdeauducq <sebastien@milkymist.org>
Wed, 11 Dec 2013 21:26:10 +0000 (22:26 +0100)
commit135a4fea25a776fcce0c8f19a23df26fcb34140c
tree90cb59b943a4ca568ee8ee26819a21d5cf510083tree
parentd6cb981c7a507ffc479abf58de36063096121d3bcommit | diff
fhdl/verilog: fix representation of negative integers

Give the explicit two's complement representation for the given bit width.

This results in less readable code compared to using unary minus,
but fixes a bug when trying to represent the most negative integer.
migen/fhdl/verilog.py diff | blob | history