arch-arm: Fix NumVecV7ArchRegs value (64->16)
authorGiacomo Travaglini <giacomo.travaglini@arm.com>
Mon, 18 Nov 2019 13:50:02 +0000 (13:50 +0000)
committerGiacomo Travaglini <giacomo.travaglini@arm.com>
Tue, 10 Dec 2019 10:15:05 +0000 (10:15 +0000)
commit1398a81618e18405afaeb31197929df2dd1cf5f4
treeeee154b18cf3aeec9d7d257d2b811772f6208d2a
parent2b72ab23abe26186403e06ce7378210a63eeff2b
arch-arm: Fix NumVecV7ArchRegs value (64->16)

In armv7 there are 16 only quadword (vector) registers which are usable
by SIMD instructions (Q0-Q15). Those completely overlap with the 32
double word registers (D0-D31).

NumVecV7ArchRegs  = 16; // Q0-Q15

Change-Id: Id8fee1064d60dcfa54f273fa7d579a20c0087835
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23105
Tested-by: kokoro <noreply+kokoro@google.com>
src/arch/arm/registers.hh