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(parent: ffd2be2) | patch
wishbone2csr: refactor using FSM, reduce latency (make it asynchronous) and set csr...
authorFlorent Kermarrec <florent@enjoy-digital.fr>
Tue, 24 Sep 2019 15:55:29 +0000 (17:55 +0200)
committerFlorent Kermarrec <florent@enjoy-digital.fr>
Tue, 24 Sep 2019 15:55:29 +0000 (17:55 +0200)
commit1425a68d9e68cd6af4508d4369512684d1b97138
treeed35f67ac1bb9a5a4805c364642108a1afcae86dtree
parentffd2be2ba077829927bfc4194f047df8d1b4d55ccommit | diff
wishbone2csr: refactor using FSM, reduce latency (make it asynchronous) and set csr.adr only when access is done (allow use of CSR/CSRBase we signal)

Making it asynchronous does not seem to deteriorate timing or resource usage, if it's the case for some designs, we'll add a register parameter.
litex/soc/interconnect/wishbone2csr.py diff | blob | history