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(parent: 8b88e26) | patch
Remove names from end record statements
authorAnton Blanchard <anton@linux.ibm.com>
Wed, 11 Sep 2019 23:04:02 +0000 (09:04 +1000)
committerAnton Blanchard <anton@ozlabs.org>
Wed, 11 Sep 2019 23:04:02 +0000 (09:04 +1000)
commit142a722ce473a53f589e0f05d7eaa66b77b0ac27
treeda599ee9f6aa217353904ca659e6f2b2b40943a0tree
parent8b88e26ecebe660263fe492a60ddb3205f8d7ca0commit | diff
Remove names from end record statements

These are optional, and vhdlpp from iverilog barfs on them.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
fpga/clk_gen_mcmm.vhd diff | blob | history
fpga/clk_gen_plle2.vhd diff | blob | history
wishbone_types.vhdl diff | blob | history