litedram: l2: Latency improvements
authorBenjamin Herrenschmidt <benh@kernel.crashing.org>
Mon, 22 Jun 2020 07:27:05 +0000 (17:27 +1000)
committerBenjamin Herrenschmidt <benh@kernel.crashing.org>
Wed, 8 Jul 2020 06:47:30 +0000 (16:47 +1000)
commit1441b2a85957f1bf6e6952621e3047348ceaa3f9
treefa2a3303a029789aa947596b10035e88a5741992
parentb0241d9f2de3dc23ed53903b296f30aee34bb5e4
litedram: l2: Latency improvements

This implements in the L2 cache the feature already in the L1s
allowing a request to be completed before the end of a refill
using partial line valid bits, and starting a refill from the
row of the first miss on that line instead of the beginning of
the line.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
dram_tb.vhdl
litedram/extras/litedram-wrapper-l2.vhdl
litedram/extras/wave_tb.gtkw