Mem: Fix issue with prefetches originating at non-L1 caches getting stale data
authorAli Saidi <Ali.Saidi@ARM.com>
Fri, 15 Jul 2011 16:53:35 +0000 (11:53 -0500)
committerAli Saidi <Ali.Saidi@ARM.com>
Fri, 15 Jul 2011 16:53:35 +0000 (11:53 -0500)
commit147095cb0886a962620e60b6950a68931fbd734a
treeb81211a4e2441c897149b4823506a60f49966a79
parent69ef57fd0f226af90faf46ac877343b5493df693
Mem: Fix issue with prefetches originating at non-L1 caches getting stale data

Prefetch requests issued from the L2 or below wouldn't check if valid data is
present higher in the system. If a prefetch into the L2 occured at the same
time as writeback from a higher-level cache the dirty data could be replaced
in by unmodified data in memory.
src/mem/cache/cache_impl.hh