dev-arm: Polish SMMUv3 CMDQ setup
authorGiacomo Travaglini <giacomo.travaglini@arm.com>
Tue, 23 Jul 2019 08:58:39 +0000 (09:58 +0100)
committerGiacomo Travaglini <giacomo.travaglini@arm.com>
Thu, 25 Jul 2019 12:49:27 +0000 (12:49 +0000)
commit15c736b2c54d78d7f18c23b09d1c9f2b25687106
tree73208f25b20c0873ea7bd7b4a6f9983db23bdc0c
parentaf1838be8d1efbbbb7133262f23f9f757033589d
dev-arm: Polish SMMUv3 CMDQ setup

The patch is aiming to be spec compliant when it comes to setup
the SMMU command queue (while CR0.CMDQEN = 0), in the following ways:

* Writes to CMDQ_CONS (read index) are allowed during initialization
* Writes to CMDQ_BASE (cmdq pointer) are allowed during initialization

According to spec,
If they happen when the command queue is in fuction (CR0.CMDQEN = 1),
behaviour is constrained unpredictable, with the following options

1) The write is ignored
2) The register takes the value and it is unpredictable whether it
affects the SMMU command queue internal state.

In the model/patch we go for option 1.

Change-Id: I1c55bc571a8b3a1c0b0a525e429ab7b1480544ff
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Michiel Van Tol <michiel.vantol@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19633
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
src/dev/arm/smmu_v3.cc