arch: ISA parser additions of vector registers
authorRekai Gonzalez-Alberquilla <Rekai.GonzalezAlberquilla@arm.com>
Wed, 5 Apr 2017 18:24:23 +0000 (13:24 -0500)
committerAndreas Sandberg <andreas.sandberg@arm.com>
Wed, 5 Jul 2017 14:43:49 +0000 (14:43 +0000)
commit166da650a3c864b31193ade893ed99e547c67644
tree84236bf28007885e864e885fab8e715e332affa6
parent00da08902918da13fccc3f2266b7b2f5d0080708
arch: ISA parser additions of vector registers

Reiley's update :) of the isa parser definitions. My addition of the
vector element operand concept for the ISA parser. Nathanael's modification
creating a hierarchy between vector registers and its constituencies to the
isa parser.

Some fixes/updates on top to consider instructions as vectors instead of
floating when they use the VectorRF. Some counters added to all the
models to keep faithful counts.

Change-Id: Id8f162a525240dfd7ba884c5a4d9fa69f4050101
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2706
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
21 files changed:
src/arch/alpha/faults.cc
src/arch/alpha/faults.hh
src/arch/alpha/isa/fp.isa
src/arch/arm/isa/insts/fp64.isa
src/arch/arm/isa/insts/neon64.isa
src/arch/arm/isa/operands.isa
src/arch/arm/isa/templates/mem.isa
src/arch/arm/isa/templates/pred.isa
src/arch/isa_parser.py
src/arch/sparc/faults.cc
src/arch/sparc/faults.hh
src/arch/sparc/isa/base.isa
src/cpu/StaticInstFlags.py
src/cpu/base_dyn_inst.hh
src/cpu/o3/commit.hh
src/cpu/o3/commit_impl.hh
src/cpu/o3/inst_queue.hh
src/cpu/o3/inst_queue_impl.hh
src/cpu/simple/base.cc
src/cpu/simple/exec_context.hh
src/cpu/static_inst.hh