i965/fs: Rework GEN5 texturing code to use fs_reg and offset()
authorJason Ekstrand <jason.ekstrand@intel.com>
Thu, 18 Sep 2014 19:16:25 +0000 (12:16 -0700)
committerJason Ekstrand <jason.ekstrand@intel.com>
Tue, 30 Sep 2014 17:29:14 +0000 (10:29 -0700)
commit16819b48ab0af244ccb5ef466a7343b1982792be
treeeb610fc0cabbb3e872d70b5f40600e53ed1e1be5
parent7210583eb84a5d49803dbe37b0960373b4224d10
i965/fs: Rework GEN5 texturing code to use fs_reg and offset()

Now that offset() can properly handle MRF registers, we can use an MRF
fs_reg and let offset() handle incrementing it correctly for different
dispatch widths.  While this doesn't have any noticeable effect currently,
it does ensure that the destination register is 16-wide which will be
necessary later when we start detecting execution sizes based on source and
destination registers.

Signed-off-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
src/mesa/drivers/dri/i965/brw_fs_visitor.cpp