Add flooring modulo operator
authorXiretza <xiretza@xiretza.xyz>
Wed, 8 Apr 2020 17:30:47 +0000 (19:30 +0200)
committerXiretza <xiretza@xiretza.xyz>
Thu, 28 May 2020 20:59:03 +0000 (22:59 +0200)
commit17163cf43a6b6eec9aac44f6a4463dda54b8ed68
tree02dd1e144c36eb40565cbb792726c7d8d4573eb4
parent0d99522b3c2ca2502129110e09f9988874e37abc
Add flooring modulo operator

The $div and $mod cells use truncating division semantics (rounding
towards 0), as defined by e.g. Verilog. Another rounding mode, flooring
(rounding towards negative infinity), can be used in e.g. VHDL. The
new $modfloor cell provides this flooring modulo (also known as "remainder"
in several languages, but this name is ambiguous).

This commit also fixes the handling of $mod in opt_expr, which was
previously optimized as if it was $modfloor.
23 files changed:
backends/btor/btor.cc
backends/btor/test_cells.sh
backends/firrtl/firrtl.cc
backends/smt2/smt2.cc
backends/smv/smv.cc
backends/smv/test_cells.sh
backends/verilog/verilog_backend.cc
kernel/calc.cc
kernel/celledges.cc
kernel/celltypes.h
kernel/rtlil.cc
kernel/rtlil.h
kernel/satgen.h
manual/PRESENTATION_Prog.tex
passes/cmds/stat.cc
passes/memory/memory_share.cc
passes/opt/opt_expr.cc
passes/opt/opt_share.cc
passes/opt/share.cc
passes/opt/wreduce.cc
passes/tests/test_cell.cc
techlibs/common/simlib.v
techlibs/common/techmap.v