Merge pull request #277 from railnova/feature/vivado_sysverilog_support
authorenjoy-digital <florent@enjoy-digital.fr>
Thu, 10 Oct 2019 17:31:09 +0000 (19:31 +0200)
committerGitHub <noreply@github.com>
Thu, 10 Oct 2019 17:31:09 +0000 (19:31 +0200)
commit17756f631bd5cd72f3b8bb577bdbb05598179d8b
tree27371701d877d211e87ffd5b9a0371e2a74a52ae
parentb25194826e21374e0fe78768098b85fccf53391b
parentf2369a4c9eeb19862dcae538d6d7f72148070a66
Merge pull request #277 from railnova/feature/vivado_sysverilog_support

[feature] Add SystemVerilog support for the Vivado builder