arch-arm: R/W interface to AArch32 HCR2 misc reg
authorAdrian Herrera <adrian.herrera@arm.com>
Fri, 8 Nov 2019 15:25:21 +0000 (15:25 +0000)
committerGiacomo Travaglini <giacomo.travaglini@arm.com>
Mon, 18 Nov 2019 15:01:01 +0000 (15:01 +0000)
commit17a0c0b00644c37e9d8539a9de0a02dc213a6834
tree8ab1d22fcfbc158dafc1a9e92a5d7562c820dc95
parent7e19b26f503435f07dc4b5675061facc521b8c91
arch-arm: R/W interface to AArch32 HCR2 misc reg

This patch implements read/write interfaces to HCR2 AArch32 register,
which is mapped to the upper 32 bits of HCR_EL2.

Change-Id: I996023f3ad8233457d19de8a506ebcf106409165
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22832
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
src/arch/arm/isa.cc
src/arch/arm/miscregs.cc
src/arch/arm/miscregs.hh
src/arch/arm/miscregs_types.hh
src/arch/arm/tracers/tarmac_parser.cc