fhdl/verilog: optionally disable clock domain creation
authorSebastien Bourdeauducq <sebastien@milkymist.org>
Mon, 18 Mar 2013 17:45:19 +0000 (18:45 +0100)
committerSebastien Bourdeauducq <sebastien@milkymist.org>
Mon, 18 Mar 2013 17:45:19 +0000 (18:45 +0100)
commit17f2b176541ea34fee2c6e7bfc37eea095127994
tree0b827ae7a4322c660ecf3eb553863b9f330091ca
parentaf4eb02551300434d676980d9877da428ad63adf
fhdl/verilog: optionally disable clock domain creation
migen/fhdl/verilog.py