hdl.dsl: add signal decoder to FSM state signal.
authorwhitequark <cz@m-labs.hk>
Wed, 26 Dec 2018 09:45:12 +0000 (09:45 +0000)
committerwhitequark <cz@m-labs.hk>
Wed, 26 Dec 2018 09:45:12 +0000 (09:45 +0000)
commit180307d06af7abf5e31d01030356a842a00b01ab
tree80b6c3669e4516206c5c7c30af9855be85c79ba6
parent8f6b20244d4830ef346986439dca88963a2d5634
hdl.dsl: add signal decoder to FSM state signal.
nmigen/hdl/dsl.py