build/sim: handle verilog $finish and if coverage is enabled, write report at the...
authorFlorent Kermarrec <florent@enjoy-digital.fr>
Thu, 20 Dec 2018 09:33:32 +0000 (10:33 +0100)
committerFlorent Kermarrec <florent@enjoy-digital.fr>
Thu, 20 Dec 2018 09:38:40 +0000 (10:38 +0100)
commit180912a7a30cd9253b5f28672aad315f253f35d6
tree0cb3c626d55bbef5de1248e5dd44c12d365fd47d
parentb6c98cab0d54491f2ddf4660f944351078b174b6
build/sim: handle verilog $finish and if coverage is enabled, write report at the end of the simulation.
litex/build/sim/core/sim.c
litex/build/sim/core/veril.cpp
litex/build/sim/core/veril.h
litex/build/sim/verilator.py