Merge pull request #2453 from YosysHQ/mmicko/verilog_assignments
authorMiodrag Milanović <mmicko@gmail.com>
Wed, 25 Nov 2020 18:15:11 +0000 (19:15 +0100)
committerGitHub <noreply@github.com>
Wed, 25 Nov 2020 18:15:11 +0000 (19:15 +0100)
commit180a8e5a45358b4d2c9b599e6838093fd121f9fd
treeb04fa3c12e34684b72ed0f416439203288472900
parentcf67e6a3977410e039d62a1e9f6c49c42cb97b08
parent7b093dca10707443d8517504fad7f5afa9eea6ca
Merge pull request #2453 from YosysHQ/mmicko/verilog_assignments

Generate only simple assignments in verilog backend