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(parent: c8033f1) | patch
i965: sandybridge pipe control workaround before write cache flush
authorZhenyu Wang <zhenyuw@linux.intel.com>
Fri, 17 Sep 2010 07:08:09 +0000 (15:08 +0800)
committerZhenyu Wang <zhenyuw@linux.intel.com>
Tue, 28 Sep 2010 07:58:21 +0000 (15:58 +0800)
commit18c3b754f974751550dc9505d50535365beac8f3
tree549c68473bf6716ecb4cd5cec80cbf687d4b97b9tree
parentc8033f1b1ea118f3f47b7f3de557b7a8dcf11082commit | diff
i965: sandybridge pipe control workaround before write cache flush

Must issue a pipe control with any non-zero post sync op before
write cache flush = 1 pipe control.
src/mesa/drivers/dri/intel/intel_batchbuffer.c diff | blob | history
src/mesa/drivers/dri/intel/intel_reg.h diff | blob | history