FDCE_1 does not have IS_CLR_INVERTED
authorEddie Hung <eddie@fpgeh.com>
Sun, 29 Sep 2019 18:25:34 +0000 (11:25 -0700)
committerEddie Hung <eddie@fpgeh.com>
Sun, 29 Sep 2019 18:25:34 +0000 (11:25 -0700)
commit18ebb86edbade4a94833dead59d69fddd980f5bd
tree488827f45c653e2daacc85c1c2ae13f50f241067
parent5a4011e8c9d2c7c94ccaa6ff80a1ca1290e1053b
FDCE_1 does not have IS_CLR_INVERTED
techlibs/xilinx/cells_sim.v