git.libre-soc.org Git - litex.git/commit

author	Florent Kermarrec <florent@enjoy-digital.fr>
	Fri, 23 Feb 2018 12:38:19 +0000 (13:38 +0100)
committer	Florent Kermarrec <florent@enjoy-digital.fr>
	Fri, 23 Feb 2018 12:38:19 +0000 (13:38 +0100)
commit	1925ba176fa7c37050c5b8e17b7fd2bd26462a18
tree	e151f5bd3f2df08d6991de6f4841130804c9a646	tree
parent	43164b9a2c1e49842a1b4b94dad5c7df66bd4c8d	commit \| diff

replace litex.gen imports with migen imports

57 files changed:

litex/boards/targets/arty.py		diff \| blob \| history
litex/boards/targets/de0nano.py		diff \| blob \| history
litex/boards/targets/kc705.py		diff \| blob \| history
litex/boards/targets/minispartan6.py		diff \| blob \| history
litex/boards/targets/nexys4ddr.py		diff \| blob \| history
litex/boards/targets/nexys_video.py		diff \| blob \| history
litex/boards/targets/sim.py		diff \| blob \| history
litex/boards/targets/simple.py		diff \| blob \| history
litex/build/altera/common.py		diff \| blob \| history
litex/build/altera/quartus.py		diff \| blob \| history
litex/build/generic_platform.py		diff \| blob \| history
litex/build/lattice/common.py		diff \| blob \| history
litex/build/lattice/diamond.py		diff \| blob \| history
litex/build/lattice/icestorm.py		diff \| blob \| history
litex/build/sim/platform.py		diff \| blob \| history
litex/build/sim/verilator.py		diff \| blob \| history
litex/build/xilinx/common.py		diff \| blob \| history
litex/build/xilinx/ise.py		diff \| blob \| history
litex/build/xilinx/vivado.py		diff \| blob \| history
litex/gen/__init__.py		diff \| blob \| history
litex/gen/fhdl/verilog.py		diff \| blob \| history
litex/gen/sim/__init__.py		diff \| blob \| history
litex/gen/sim/core.py		diff \| blob \| history
litex/gen/sim/vcd.py		diff \| blob \| history
litex/soc/cores/code_8b10b.py		diff \| blob \| history
litex/soc/cores/cordic.py		diff \| blob \| history
litex/soc/cores/cpu/lm32/core.py		diff \| blob \| history
litex/soc/cores/cpu/mor1kx/core.py		diff \| blob \| history
litex/soc/cores/cpu/picorv32/core.py		diff \| blob \| history
litex/soc/cores/dna.py		diff \| blob \| history
litex/soc/cores/frequency_meter.py		diff \| blob \| history
litex/soc/cores/gpio.py		diff \| blob \| history
litex/soc/cores/identifier.py		diff \| blob \| history
litex/soc/cores/nor_flash_16.py		diff \| blob \| history
litex/soc/cores/spi.py		diff \| blob \| history
litex/soc/cores/spi_flash.py		diff \| blob \| history
litex/soc/cores/timer.py		diff \| blob \| history
litex/soc/cores/uart.py		diff \| blob \| history
litex/soc/cores/xadc.py		diff \| blob \| history
litex/soc/integration/cpu_interface.py		diff \| blob \| history
litex/soc/integration/sdram_init.py		diff \| blob \| history
litex/soc/integration/soc_core.py		diff \| blob \| history
litex/soc/integration/soc_sdram.py		diff \| blob \| history
litex/soc/interconnect/axi.py		diff \| blob \| history
litex/soc/interconnect/csr.py		diff \| blob \| history
litex/soc/interconnect/csr_bus.py		diff \| blob \| history
litex/soc/interconnect/csr_eventmanager.py		diff \| blob \| history
litex/soc/interconnect/stream.py		diff \| blob \| history
litex/soc/interconnect/stream_packet.py		diff \| blob \| history
litex/soc/interconnect/stream_sim.py		diff \| blob \| history
litex/soc/interconnect/wishbone.py		diff \| blob \| history
litex/soc/interconnect/wishbone2csr.py		diff \| blob \| history
litex/soc/interconnect/wishbonebridge.py		diff \| blob \| history
test/test_bitslip.py		diff \| blob \| history
test/test_code_8b10b.py		diff \| blob \| history
test/test_gearbox.py		diff \| blob \| history
test/test_targets.py		diff \| blob \| history

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