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(parent: 6576416) | patch
integration/soc/add_sdram: allow the CPU to add the direct memory buses when adding...
authorFlorent Kermarrec <florent@enjoy-digital.fr>
Wed, 29 Jul 2020 09:10:05 +0000 (11:10 +0200)
committerFlorent Kermarrec <florent@enjoy-digital.fr>
Wed, 29 Jul 2020 09:10:05 +0000 (11:10 +0200)
commit1938ce363d21b6a21678ab4dfa9f84eb622417a6
tree2ebc68c5a2b6d94ed3188edc02af918e8505082dtree
parent6576416b8e918b86c2e739457b5feea0144bd8a3commit | diff
integration/soc/add_sdram: allow the CPU to add the direct memory buses when adding the sdram.

This is useful for CPUs elaborated at buildtime to use sdram's native data width on the CPU memory ports.
litex/soc/integration/soc.py diff | blob | history