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(parent: 2c07e03) | patch
iris: implement gen12 post sync pipe control workaround
authorLionel Landwerlin <lionel.g.landwerlin@intel.com>
Wed, 15 Jan 2020 12:06:07 +0000 (14:06 +0200)
committerMarge Bot <eric+marge@anholt.net>
Wed, 5 Feb 2020 00:25:48 +0000 (00:25 +0000)
commit19e7bcee1742a40981a0b1c06447bca22646c294
tree05f8872902569e1ee04308bcd2b2b271c972e2d4tree
parent2c07e03b792d57ae807a6953f0d8ff5f4bcdffd0commit | diff
iris: implement gen12 post sync pipe control workaround

Like Skylake, Gen12 requires a workaround for PIPE_CONTROLs using a
post-sync operation.

v2: Restrict to A0

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3405>
src/gallium/drivers/iris/iris_state.c diff | blob | history