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(parent: 7c3f7b4) | patch
back.rtlil: refuse to create extremely large wires.
authorwhitequark <whitequark@whitequark.org>
Mon, 13 Apr 2020 16:38:36 +0000 (16:38 +0000)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Fri, 31 Dec 2021 13:27:09 +0000 (13:27 +0000)
commit1a88e489a5e02dfbd58a684469950fd5ead6b4dd
treeaee44e5facbf60b625075f3f83eaf7c9f2997885tree
parent7c3f7b46a6b0af56aedd5fbed7552cda0d9777dacommit | diff
back.rtlil: refuse to create extremely large wires.

Such wires are likely to trigger pathological behavior in Yosys and,
if applicable, other toolchains that consume Verilog converted from
RTLIL.

Fixes #341.
nmigen/back/rtlil.py diff | blob | history