bring bram signals out to top_level, initially for debugging purposes
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Thu, 30 Dec 2021 21:25:53 +0000 (21:25 +0000)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Thu, 30 Dec 2021 21:25:53 +0000 (21:25 +0000)
commit1ad0b014fd7b5f24498533876fd0061ecacd8c52
tree4a78e36edf5bc4a49afc7e0be0768ec263d9f8cb
parentf636bb7c3999d9326a2bd1c6131fc128be2cae24
bring bram signals out to top_level, initially for debugging purposes
and ultimately with the purpose of replacing compiled-in verilator hex
dumps with reading/writing a file directly in the main verilator loop

Signed-off-by: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Makefile
fpga/top-generic.vhdl
soc.vhdl
verilator/microwatt-verilator.cpp
wishbone_bram_wrapper.vhdl