fix dsrd pseudocode for new 3-in 2-out
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Thu, 27 Oct 2022 14:47:53 +0000 (15:47 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Fri, 28 Oct 2022 07:33:22 +0000 (08:33 +0100)
commit1af6102a153302cda4674adab51cdff1f7b9069a
tree5c2082cfef9d6a7be1b06064be4b1dfded63d1cb
parent1ffcbeef7c072908c06c4fbdb16da3a7862517eb
fix dsrd pseudocode for new 3-in 2-out
https://bugs.libre-soc.org/show_bug.cgi?id=937#c16
openpower/isa/svfixedarith.mdwn
src/openpower/test/bigint/bigint_cases.py