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re PR target/14552 (compiled trivial vector intrinsic code is inefficient)
authorUros Bizjak <ubizjak@gmail.com>
Wed, 19 Mar 2008 23:38:35 +0000 (00:38 +0100)
committerUros Bizjak <uros@gcc.gnu.org>
Wed, 19 Mar 2008 23:38:35 +0000 (00:38 +0100)
commit1b1d8f8817fdc22a84c1cee4905192f15bb2df52
tree6bc9c1ea888993833865ad22b0865a8630af51eetree
parent05e6ee933ee2acec2477fedb6b22a08ffc2431bfcommit | diff
re PR target/14552 (compiled trivial vector intrinsic code is inefficient)

        PR target/14552
        * config/i386/mmx.md (*mov<mode>_internal_rex64"): Adjust register
        allocator preferences for "y" and "r" class registers.
        ("*mov<mode>_internal"): Ditto.
        ("*movv2sf_internal_rex64"): Ditto.
        ("*movv2sf_internal"): Ditto.

testsuite/ChangeLog:

        PR target/14552
        * gcc.target/i386/pr14552.c: New test.

From-SVN: r133354
gcc/ChangeLog diff | blob | history
gcc/config/i386/mmx.md diff | blob | history
gcc/testsuite/ChangeLog diff | blob | history
gcc/testsuite/gcc.target/i386/pr14552.c [new file with mode: 0644] blob