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(parent: 3c6e66d) | patch
Fix count-leading/trailing-zeroes
authorAnton Blanchard <anton@linux.ibm.com>
Thu, 10 Oct 2019 03:36:23 +0000 (14:36 +1100)
committerAnton Blanchard <anton@ozlabs.org>
Thu, 10 Oct 2019 05:05:34 +0000 (16:05 +1100)
commit1b559aee31b539d3692ca2198f6419cba08704fc
treea2463a5ede072c3e97d8c85355d9c20d205af687tree
parent3c6e66dc9612d677786aec6fed22568f46183813commit | diff
Fix count-leading/trailing-zeroes

The current code simulates correctly, but produces miscompares when synthesized
onto an FPGA. On closer inspection GHDL synthesis complains about inferred
latches and there does seem to be issues.

Convert it to variables that are always initialized to zero at the start of the
process.

Fixes: 24a4a796ce1e ("execute: Consolidate count-leading/trailing-zeroes implementations")
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
countzero.vhdl diff | blob | history