git.libre-soc.org Git - gem5.git/commit

author	Yasuko Eckert <yasuko.eckert@amd.com>
	Tue, 15 Oct 2013 18:22:44 +0000 (14:22 -0400)
committer	Yasuko Eckert <yasuko.eckert@amd.com>
	Tue, 15 Oct 2013 18:22:44 +0000 (14:22 -0400)
commit	1bb293d1e7a27e306ca584a3922f2fd13481e248
tree	21d457f5c7d7e2e836eaf944b7d82964fc64d1bd	tree
parent	2c293823aa7cb6d2cac4c0ff35e2023ff132a8f2	commit \| diff

arch/x86: add support for explicit CC register file

Convert condition code registers from being specialized
("pseudo") integer registers to using the recently
added CC register class.

Nilay Vaish also contributed to this patch.

src/arch/x86/isa/operands.isa		diff \| blob \| history
src/arch/x86/registers.hh		diff \| blob \| history
src/arch/x86/regs/ccr.hh	[new file with mode: 0644]	blob
src/arch/x86/regs/int.hh		diff \| blob \| history
src/arch/x86/utility.cc		diff \| blob \| history
src/arch/x86/x86_traits.hh		diff \| blob \| history
src/cpu/o3/O3CPU.py		diff \| blob \| history

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