dcache: Remove dependency of r1.wb.adr/dat/sel on req_op
authorPaul Mackerras <paulus@ozlabs.org>
Fri, 10 Jul 2020 23:10:24 +0000 (09:10 +1000)
committerPaul Mackerras <paulus@ozlabs.org>
Tue, 14 Jul 2020 23:48:43 +0000 (09:48 +1000)
commit1be6fbac3333a7f99c0cf7151100e8032f4cea50
tree3b03d958251c36c9bc74b9cbf6619ffa95169907
parentc01e1c7b91068e04751b19b8b22e4c452c94080b
dcache:  Remove dependency of r1.wb.adr/dat/sel on req_op

This improves timing by setting r1.wb.{adr,dat,sel} to the next
request when doing a write cycle on the wishbone before we know
whether the next request has a TLB and cache hit or not, i.e.
without depending on req_op.  r1.wb.stb still depends on req_op.

This contains a workaround for what is probably a bug elsewhere,
in that changing r1.wb.sel unconditionally once we see stall=0
from the wishbone causes incorrect behaviour.  Making it
conditional on there being a valid following request appears
to fix the problem.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
dcache.vhdl