Added module->ports
authorClifford Wolf <clifford@clifford.at>
Thu, 14 Aug 2014 14:13:42 +0000 (16:13 +0200)
committerClifford Wolf <clifford@clifford.at>
Thu, 14 Aug 2014 14:22:52 +0000 (16:22 +0200)
commit1bf7a18fec76cf46a5b8710a75371e23b68d147d
treeea445edda6c4bc0fa670effce4ef1b0eaf906258
parent746aac540b815099c6a63077010555369d7fdd5a
Added module->ports
frontends/ast/ast.cc
frontends/ilang/parser.y
kernel/celltypes.h
kernel/rtlil.cc
kernel/rtlil.h
passes/abc/blifparse.cc
passes/hierarchy/hierarchy.cc
passes/hierarchy/submod.cc
passes/techmap/extract.cc