sim/riscv: fix JALR instruction simulation
authorJaydeep Patil <Jaydeep.Patil@imgtec.com>
Wed, 18 Oct 2023 16:37:59 +0000 (17:37 +0100)
committerAndrew Burgess <aburgess@redhat.com>
Wed, 18 Oct 2023 16:55:31 +0000 (17:55 +0100)
commit1c37b30945073f34bbb685d2ac47ab01e0c93d45
tree6a930551898f502f4fcaabfc60b03bf6b9544432
parent29736fc507c7a9c6e797b7f83e8df4be73d37767
sim/riscv: fix JALR instruction simulation

Fix 32bit 'jalr rd,ra,imm' integer instruction, where RD was written
before using it to calculate destination address.

This commit also improves testutils.inc for riscv; make use of
pushsection and popsection when adding things to .data, and setup the
%gp global pointer register within the 'start' macro.

Approved-By: Andrew Burgess <aburgess@redhat.com>
sim/riscv/sim-main.c
sim/testsuite/riscv/jalr.s [new file with mode: 0644]
sim/testsuite/riscv/testutils.inc