projects / yosys.git / commit
| author | Clifford Wolf <clifford@clifford.at> | |
| Thu, 31 Mar 2016 06:43:28 +0000 (08:43 +0200) | ||
| committer | Clifford Wolf <clifford@clifford.at> | |
| Thu, 31 Mar 2016 06:46:56 +0000 (08:46 +0200) | ||
| commit | 1d0f0d668ade740c928c66c400476924abf62384 | |
| tree | 8215e3fb7c6fd92a8560217e0840a90a39a620e6 | tree |
| parent | d31c968d76e99d5c7288d0eb844e041bb36aa77d | commit | diff |
| backends/btor/verilog2btor.sh | diff | blob | history | |
| manual/APPNOTE_012_Verilog_to_BTOR.tex | diff | blob | history | |
| manual/CHAPTER_Optimize.tex | diff | blob | history | |
| manual/CHAPTER_Overview.tex | diff | blob | history | |
| manual/PRESENTATION_ExSyn.tex | diff | blob | history | |
| passes/opt/Makefile.inc | diff | blob | history | |
| passes/opt/opt.cc | diff | blob | history | |
| passes/opt/opt_const.cc | [deleted file] | blob | history |
| passes/opt/opt_expr.cc | [new file with mode: 0644] | blob |
| passes/sat/miter.cc | diff | blob | history | |
| techlibs/common/prep.cc | diff | blob | history | |
| techlibs/common/synth.cc | diff | blob | history | |
| techlibs/common/techmap.v | diff | blob | history | |
| techlibs/ice40/ice40_opt.cc | diff | blob | history | |
| techlibs/ice40/synth_ice40.cc | diff | blob | history |