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(parent: eff18a2) | patch
verlog: allow shadowing module ports within generate blocks
authorZachary Snow <zach@zachjs.com>
Sun, 7 Feb 2021 04:54:17 +0000 (23:54 -0500)
committerZachary Snow <zach@zachjs.com>
Sun, 7 Feb 2021 16:48:39 +0000 (11:48 -0500)
commit1d5f3fe5064146955dafdabafe7180ff79c95d08
treeccc9c6a40e9ea885b693f6c2e51202f4217453d2tree
parenteff18a2b1519428b11400979f116342086c13e13commit | diff
verlog: allow shadowing module ports within generate blocks

This is a somewhat obscure edge case I encountered while working on test
cases for earlier changes. Declarations in generate blocks should not be
checked against the list of ports. This change also adds a check
forbidding declarations within generate blocks being tagged as inputs or
outputs.
frontends/verilog/verilog_parser.y diff | blob | history
tests/simple/genblk_port_shadow.v [new file with mode: 0644] blob
tests/verilog/genblk_port_decl.ys [new file with mode: 0644] blob