hdl.ir: allow ClockSignal and ResetSignal in ports.
authorwhitequark <cz@m-labs.hk>
Sun, 13 Oct 2019 03:39:56 +0000 (03:39 +0000)
committerwhitequark <cz@m-labs.hk>
Sun, 13 Oct 2019 03:39:56 +0000 (03:39 +0000)
commit1de77632e8096eeca02044a48b1a4b5144f0279b
tree30d0789ea525a8943a9c35461248d63fa2bc8d64
parentfde6cff119253f6792c3195c9ae42eebfcfd371f
hdl.ir: allow ClockSignal and ResetSignal in ports.

Fixes #248.
nmigen/hdl/ir.py
nmigen/hdl/xfrm.py
nmigen/test/test_hdl_ir.py