Added note about SystemVerilog assert statement to README
authorClifford Wolf <clifford@clifford.at>
Sat, 1 Feb 2014 12:04:49 +0000 (13:04 +0100)
committerClifford Wolf <clifford@clifford.at>
Sat, 1 Feb 2014 12:04:49 +0000 (13:04 +0100)
commit1e2440e7ed6979bdee2f80116d6c3a429b604e25
treebd85ea941530962efb0d51b942e17f3b5dcc0e4c
parentfa92722358f156a1e4b99d3ba4e0900e0a771116
Added note about SystemVerilog assert statement to README
README