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(parent: 4c9fde8) | patch
Retry "Add "-W' wire delay arg to abc9, use from synth_xilinx"
authorEddie Hung <eddie@fpgeh.com>
Wed, 12 Jun 2019 15:49:15 +0000 (08:49 -0700)
committerEddie Hung <eddie@fpgeh.com>
Wed, 12 Jun 2019 15:49:15 +0000 (08:49 -0700)
commit1e838a8913afa36a57d425f26ea881f5071b8b5d
treec46b5e6f6f0f94a55f6601193f98b3ca9d83ff50tree
parent4c9fde87d170fc8d4b729581b055407553951e4ccommit | diff
Retry "Add "-W' wire delay arg to abc9, use from synth_xilinx"
passes/techmap/abc9.cc diff | blob | history
techlibs/xilinx/synth_xilinx.cc diff | blob | history