Added non-std verilog assume() statement
authorClifford Wolf <clifford@clifford.at>
Thu, 26 Feb 2015 17:47:39 +0000 (18:47 +0100)
committerClifford Wolf <clifford@clifford.at>
Thu, 26 Feb 2015 17:47:39 +0000 (18:47 +0100)
commit1f1deda888ea32ade2478fca9fcb510ada477606
treebf21e5e60e970745af2d4652addfbe383f6b4187
parentb005eedf369bc60ce5f7cba9a0db4694f22a360f
Added non-std verilog assume() statement
frontends/ast/ast.cc
frontends/ast/ast.h
frontends/ast/genrtlil.cc
frontends/ast/simplify.cc
frontends/verilog/verilog_frontend.cc
frontends/verilog/verilog_frontend.h
frontends/verilog/verilog_lexer.l
frontends/verilog/verilog_parser.y
passes/opt/opt_clean.cc
passes/sat/sat.cc