Merge pull request #802 from whitequark/write_verilog_async_mem_ports
authorClifford Wolf <clifford@clifford.at>
Tue, 12 Feb 2019 13:41:34 +0000 (14:41 +0100)
committerGitHub <noreply@github.com>
Tue, 12 Feb 2019 13:41:34 +0000 (14:41 +0100)
commit1f2548a564812d55b8263020d5fe9e92368f818e
treec009f74a9620fbae87e519131ec869b1ff1e96f1
parentb9f6ed40b68f3065077267313ecc07c267b43716
parentda65e1e8d9552f64e1e03c08108ca0532719bbfe
Merge pull request #802 from whitequark/write_verilog_async_mem_ports

write_verilog: correctly emit asynchronous transparent ports