projects / yosys.git / commit
? search:
summary | shortlog | log | commit | commitdiff | tree
(parent: ce4a095) | patch
Added tests for Verilog frontent for attributes on parameters and localparams
authorMaciej Kurc <mkurc@antmicro.com>
Thu, 16 May 2019 10:53:43 +0000 (12:53 +0200)
committerMaciej Kurc <mkurc@antmicro.com>
Thu, 16 May 2019 10:53:43 +0000 (12:53 +0200)
commit1f52332b8d4621d6c5ab1447e82b6e2e53600e52
tree9977477bebc1105ca0cf2b82c79e092faa66d832tree
parentce4a0954bc896eedfc2d87e2c9d2b40f42a101dbcommit | diff
Added tests for Verilog frontent for attributes on parameters and localparams

Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
tests/simple/localparam_attr.v [new file with mode: 0644] blob
tests/simple/param_attr.v [new file with mode: 0644] blob