git.libre-soc.org Git - gem5.git/commit

author	Alexandru Dutu <alexandru.dutu@amd.com>
	Mon, 24 Nov 2014 02:01:09 +0000 (18:01 -0800)
committer	Alexandru Dutu <alexandru.dutu@amd.com>
	Mon, 24 Nov 2014 02:01:09 +0000 (18:01 -0800)
commit	1f539f13c32ad5a9187d56a098d4c857639b0e05
tree	7618c3b946d9c25d9b22018f226eee77b6de4aaf	tree
parent	c11bcb8119273ef91c40a25b8fd9471a887d0ee5	commit \| diff

mem: Page Table map api modification

This patch adds uncacheable/cacheable and read-only/read-write attributes to
the map method of PageTableBase. It also modifies the constructor of TlbEntry
structs for all architectures to consider the new attributes.

14 files changed:

RSS Atom

src/arch/alpha/pagetable.hh		diff \| blob \| history
src/arch/arm/pagetable.hh		diff \| blob \| history
src/arch/mips/pagetable.hh		diff \| blob \| history
src/arch/power/tlb.hh		diff \| blob \| history
src/arch/sparc/pagetable.hh		diff \| blob \| history
src/arch/x86/pagetable.cc		diff \| blob \| history
src/arch/x86/pagetable.hh		diff \| blob \| history
src/mem/multi_level_page_table.hh		diff \| blob \| history
src/mem/multi_level_page_table_impl.hh		diff \| blob \| history
src/mem/page_table.cc		diff \| blob \| history
src/mem/page_table.hh		diff \| blob \| history
src/sim/Process.py		diff \| blob \| history
src/sim/process.cc		diff \| blob \| history
src/sim/process.hh		diff \| blob \| history