mem: Rename Bus to XBar to better reflect its behaviour
authorAndreas Hansson <andreas.hansson@arm.com>
Sat, 20 Sep 2014 21:18:32 +0000 (17:18 -0400)
committerAndreas Hansson <andreas.hansson@arm.com>
Sat, 20 Sep 2014 21:18:32 +0000 (17:18 -0400)
commit1f6d5f8f849f50a3646f586b1274708537124ef3
tree03c98c46d500fbd9ac8135baea399813ea3d5644
parent1884bcc03ba2b6e734b4bd379d8542596e6d5c84
mem: Rename Bus to XBar to better reflect its behaviour

This patch changes the name of the Bus classes to XBar to better
reflect the actual timing behaviour. The actual instances in the
config scripts are not renamed, and remain as e.g. iobus or membus.

As part of this renaming, the code has also been clean up slightly,
making use of range-based for loops and tidying up some comments. The
only changes outside the bus/crossbar code is due to the delay
variables in the packet.

--HG--
rename : src/mem/Bus.py => src/mem/XBar.py
rename : src/mem/coherent_bus.cc => src/mem/coherent_xbar.cc
rename : src/mem/coherent_bus.hh => src/mem/coherent_xbar.hh
rename : src/mem/noncoherent_bus.cc => src/mem/noncoherent_xbar.cc
rename : src/mem/noncoherent_bus.hh => src/mem/noncoherent_xbar.hh
rename : src/mem/bus.cc => src/mem/xbar.cc
rename : src/mem/bus.hh => src/mem/xbar.hh
47 files changed:
configs/common/CacheConfig.py
configs/common/FSConfig.py
configs/dram/sweep.py
configs/example/memtest.py
configs/example/ruby_mem_test.py
configs/example/se.py
configs/splash2/cluster.py
configs/splash2/run.py
src/arch/x86/pagetable_walker.cc
src/cpu/BaseCPU.py
src/dev/io_device.cc
src/dev/pcidev.cc
src/dev/x86/intdev.hh
src/mem/Bus.py [deleted file]
src/mem/SConscript
src/mem/XBar.py [new file with mode: 0644]
src/mem/bridge.cc
src/mem/bridge.hh
src/mem/bus.cc [deleted file]
src/mem/bus.hh [deleted file]
src/mem/cache/cache_impl.hh
src/mem/coherent_bus.cc [deleted file]
src/mem/coherent_bus.hh [deleted file]
src/mem/coherent_xbar.cc [new file with mode: 0644]
src/mem/coherent_xbar.hh [new file with mode: 0644]
src/mem/dram_ctrl.cc
src/mem/dramsim2.cc
src/mem/noncoherent_bus.cc [deleted file]
src/mem/noncoherent_bus.hh [deleted file]
src/mem/noncoherent_xbar.cc [new file with mode: 0644]
src/mem/noncoherent_xbar.hh [new file with mode: 0644]
src/mem/packet.hh
src/mem/physical.cc
src/mem/simple_mem.cc
src/mem/xbar.cc [new file with mode: 0644]
src/mem/xbar.hh [new file with mode: 0644]
src/python/m5/params.py
src/python/m5/util/dot_writer.py
tests/configs/base_config.py
tests/configs/memtest-filter.py
tests/configs/memtest-ruby.py
tests/configs/memtest.py
tests/configs/o3-timing-mp-ruby.py
tests/configs/o3-timing-ruby.py
tests/configs/simple-atomic-mp-ruby.py
tests/configs/tgen-dram-ctrl.py
tests/configs/tgen-simple-mem.py