projects / yosys.git / commit
| author | dh73 <dh73_fpga@qq.com> | |
| Thu, 9 Nov 2017 02:23:55 +0000 (20:23 -0600) | ||
| committer | dh73 <dh73_fpga@qq.com> | |
| Thu, 9 Nov 2017 02:23:55 +0000 (20:23 -0600) | ||
| commit | 1fc061d90c45166f87d92f76b6fae1ec517be72f | |
| tree | b7c0418b904bfe2e730d6a29cadabdcfcf416496 | tree |
| parent | adf17547290b403e863ed7c71960a5678c6bbfaf | commit | diff |
| techlibs/achronix/Makefile.inc | diff | blob | history | |
| techlibs/achronix/speedster22i/cells_arith.v | [new file with mode: 0755] | blob |
| techlibs/achronix/speedster22i/cells_arith_speedster.v | [deleted file] | blob | history |
| techlibs/achronix/speedster22i/cells_comb_speedster.v | [deleted file] | blob | history |
| techlibs/achronix/speedster22i/cells_map.v | [new file with mode: 0755] | blob |
| techlibs/achronix/speedster22i/cells_map_speedster.v | [deleted file] | blob | history |
| techlibs/achronix/speedster22i/cells_sim.v | [new file with mode: 0755] | blob |
| techlibs/achronix/synth_speedster.cc | diff | blob | history |