i965: Work around L3 state leaks during context switches.
authorFrancisco Jerez <currojerez@riseup.net>
Thu, 3 Sep 2015 15:23:19 +0000 (18:23 +0300)
committerFrancisco Jerez <currojerez@riseup.net>
Wed, 9 Dec 2015 11:57:40 +0000 (13:57 +0200)
commit1fc797e8e408522cfbd3fa9f81d4fb33acccb034
treea4d5555f197a5985e69346ac7326a61221b19f31
parent09d9638dd04ae7d34d331cb7af0bc5888f48806f
i965: Work around L3 state leaks during context switches.

This is going to require some rather intrusive kernel changes to fix
properly, in the meantime (and forever on at least pre-v4.1 kernels)
we'll have to restore the hardware defaults at the end of every batch
in which the L3 configuration was changed to avoid interfering with
the DDX and GL clients that use an older non-L3-aware version of Mesa.

Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
v2: Optimize look-up of the default configuration by assuming it's the
    first entry of the L3 config array in order to avoid an FPS
    regression in GpuTest Triangle and SynMark OglBatch2-7 on most
    affected platforms.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
src/mesa/drivers/dri/i965/brw_state.h
src/mesa/drivers/dri/i965/gen7_l3_state.c
src/mesa/drivers/dri/i965/intel_batchbuffer.c
src/mesa/drivers/dri/i965/intel_batchbuffer.h