vexriscv: verilog: pull debug-enabled verilog
authorSean Cross <sean@xobs.io>
Thu, 28 Jun 2018 01:24:34 +0000 (09:24 +0800)
committerSean Cross <sean@xobs.io>
Thu, 5 Jul 2018 09:25:27 +0000 (17:25 +0800)
commit2024542a3c8d14c9daeb53c912cd0bda43f73abc
tree0bb7cb4ed777a8e175034e7a6b26317294c3b32b
parentfa0215660bc34b7becdea416531ae6e30396ce4a
vexriscv: verilog: pull debug-enabled verilog

The upstream vexriscv repo now generates both the current VexRiscv.v
softcore, as well as VexRiscv-Debug.v.  This -Debug varient exposes
their specialized debug bus that allows for attaching a modified version
of openocd.

Sync the litex repo with the upstream version to take advantage of debug
support.

Signed-off-by: Sean Cross <sean@xobs.io>
litex/soc/cores/cpu/vexriscv/verilog